View AD9912ABCPZ_6518492.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 gsps direct digital synthesizer with 14-bit dac ad9912 rev. f information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007C2010 analog devices, inc. all rights reserved. features 1 gsps internal clock speed (up to 400 mhz output directly) integrated 1 gsps 14-bit dac 48-bit frequency tuning word with 4 hz resolution differential hstl comparator flexible system clock input accepts either crystal or external reference clock on-chip low noise pll refclk multiplier 2 spurkiller channels low jitter clock doubler for frequencies up to 750 mhz single-ended cmos comparator; frequencies of <150 mhz programmable output divider for cmos output serial i/o control excellent dynamic performance software controlled power-down available in two 64-lead lfcsp packages residual phase noise @ 250 mhz 10 hz offset: ?113 dbc/hz 1 khz offset: ?133 dbc/hz 100 khz offset: ?153 dbc/hz 40 mhz offset: ?161 dbc/hz applications agile lo frequency synthesis low jitter, fine tune clock generation test and measurement equipment wireless base stations and controllers secure communications fast frequency hopping general description the ad9912 is a direct digital synthesizer (dds) that features an integrated 14-bit digital-to-analog converter (dac). the ad9912 features a 48-bit frequency tuning word (ftw) that can synthesize frequencies in step sizes no larger than 4 hz. absolute frequency accuracy can be achieved by adjusting the dac system clock. the ad9912 also features an integrated system clock phase- locked loop (pll) that allows for system clock inputs as low as 25 mhz. the ad9912 operates over an industrial temperature range, spanning ?40c to +85c. basic block diagram fdbk_in dac_out ad9912 s1 to s4 out out_cmos filter system clock multiplier serial port, i/o logic clock output drivers digital interface 06763-001 direct digital synthesis core startup configuration logic figure 1.
ad9912 rev. f | page 2 of 40 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 basic block diagram ........................................................................ 1 revision history ............................................................................... 3 specifications ..................................................................................... 4 dc specifications ......................................................................... 4 ac specifications .......................................................................... 6 absolute maximum ratings ............................................................ 8 thermal resistance ...................................................................... 8 esd caution .................................................................................. 8 pin configuration and function descriptions ............................. 9 typical performance characteristics ........................................... 11 input/output termination recommendations .......................... 16 theory of operation ...................................................................... 17 overview ...................................................................................... 17 direct digital synthesizer (dds) ............................................. 17 digital-to-analog (dac) output ............................................ 18 reconstruction filter ................................................................. 18 fdbk_in inputs ........................................................................ 19 sysclk inputs ........................................................................... 20 output clock drivers and 2 frequency multiplier ............. 22 harmonic spur reduction ........................................................ 22 thermal performance .................................................................... 24 power-up ......................................................................................... 25 power-on reset .......................................................................... 25 default output frequency on power-up ................................ 25 power supply partitioning ............................................................. 26 3.3 v supplies .............................................................................. 26 1.8 v supplies .............................................................................. 26 serial control port ......................................................................... 27 serial control port pin descriptions ....................................... 27 operation of serial control port .............................................. 27 the instruction word (16 bits) ................................................ 28 msb/lsb first transfers ........................................................... 28 i/o register map ............................................................................ 31 i/o register descriptions .............................................................. 33 serial port configuration (register 0x0000 to register 0x0005) ......................................................................... 33 power-down and reset (register 0x0010 to register 0x0013) ......................................................................... 33 system clock (register 0x0020 to register 0x0022) ............. 34 cmos output divider (s-divider) (register 0x0100 to register 0x0106) ......................................................................... 35 frequency tuning word (register 0x01a0 to register 0x01ad) ....................................................................... 35 doubler and output drivers (register 0x0200 to register 0x0201) ......................................................................... 37 calibration (user-accessible trim) (register 0x0400 to register 0x0410) ......................................................................... 37 harmonic spur reduction (register 0x0500 to register 0x0509) ......................................................................... 37 outline dimensions ....................................................................... 39 ordering guide .......................................................................... 39
ad9912 rev. f | page 3 of 40 revision history 6/10rev. e to rev. f changed default value of register 0x003 to 0x19 ( table 12) ..... 31 5/10rev. d to rev. e deleted 64-lead lfcsp (cp-64-1) .................................. universal changes to sysclk pll enabled/ maximum input rate of system clock pfd, table 2 ............................................................................... 6 updated outline dimensions ........................................................ 39 changes to ordering guide ........................................................... 39 11/09rev. c to rev. d added 64-lead lfcsp (cp-64-7) .................................... universal changes to serial port timing specifications and propagation delay parameters ........................................................ 6 added exposed paddle notation to figure 2 ................................ 8 changes to power supply partitioning section ........................... 25 change to serial control port section ......................................... 26 changes to figure 52 ...................................................................... 28 added exposed paddle notation to outline dimensions ......... 38 changes to ordering guide ........................................................... 39 7/09rev. b to rev. c changes to logic outputs parameter, table 1 .............................. 3 changes to avdd (pin 25, pin 26, pin 29, and pin 30) ............ 25 6/09rev. a to rev. b changes to figure 40 and direct digital synthesizer section .. 17 changes to figure 48 ...................................................................... 22 changes to table 11 ........................................................................ 30 changes to table 22 and table 23 ................................................. 34 1/08rev. 0 to rev. a changes to table 1 ............................................................................ 3 changes to table 2 ............................................................................ 5 changes to table 4 ............................................................................ 8 changes to typical performance characteristics ....................... 10 changes to functional description section ................................ 19 changes to single-ended cmos output section ...................... 21 changes to harmonic spur reduction section .......................... 21 changes to power supply partitioning section ........................... 25 10/07revision 0: initial version
ad9912 rev. f | page 4 of 40 specifications dc specifications avdd = 1.8 v 5%, avdd3 = 3.3 v 5%, dvdd = 1.8 v 5%, dvdd_i/o = 3.3 v 5%, avss = 0 v, dvss = 0 v, unless otherwise noted . table 1. parameter min typ max unit test conditions/comments supply voltage dvdd_i/o (pin 1) 3.135 3.30 3.465 v dvdd (pin 3, pin 5, pin 7) 1.71 1.80 1.89 v avdd3 (pin 14, pin 46, pin 47, pin 49) 3.135 3.30 3.465 v avdd3 (pin 37) 1.71 3.30 3.465 v pin 37 is typically 3.3 v but can be set to 1.8 v avdd (pin 11, pin 19, pin 23 to pin 26, pin 29, pin 30, pin 36, pin 42, pin 44, pin 45, pin 53) 1.71 1.80 1.89 v supply current see also the total power dissipation specifications i avdd3 (pin 37) 8 9.6 ma cmos output driver at 3.3 v, 50 mhz, with 5 pf load i avdd3 (pin 46, pin 47, pin 49) 26 31 ma dac output current source, f s = 1 gsps i avdd (pin 11, pin 19, pin 23 to pin 26, pin 29, pin 30, pin 36, pin 42, pin 44, pin 45) 113 136 ma aggregate analog supply, with system clock pll, hstl output driver, and s-divider enabled i avdd (pin 53) 40 48 ma dac power supply i dvdd (pin 3, pin 5, pin 7) 205 246 ma digital core (spurkiller off ) i dvdd_i/o (pin 1, pin 14 1 ) 2 3 ma digital i/o (varies dynamically) logic inputs (except pin 32) pin 9, pin 10, pin 54, pin 55, pin 58 to pin 61, pin 63, pin 64 input high voltage (v ih ) 2.0 dvdd_i/o v input low voltage (v il ) dvss 0.8 v input current (i inh , i inl ) 60 200 a at v in = 0 v and v in = dvdd_i/o maximum input capacitance (c in ) 3 pf clkmodesel (pin 32) logic input pin 32 only input high voltage (v ih ) 1.4 avdd v input low voltage (v il ) avss 0.4 v input current (i inh , i inl ) ?18 ?50 a at v in = 0 v and v in = avdd maximum input capacitance (c in ) 3 pf logic outputs pin 62 and the following bidirectional pins: pin 9, pin 10, pin 54, pin 55, pin 63 output high voltage (v oh ) 2.7 dvdd_i/o v i oh = 1 ma output low voltage (v ol ) dvss 0.4 v i ol = 1 ma fdbk_in input pin 40, pin 41 input capacitance 3 pf input resistance 18 22 26 k differential differential input voltage swing 225 mv p-p equivalent to 112.5 mv swing on each leg; must be ac-coupled
ad9912 rev. f | page 5 of 40 parameter min typ max unit test conditions/comments system clock input system clock inputs should always be ac- coupled (both single-ended and differential) sysclk pll bypassed input capacitance 1.5 pf single-ended, each pin input resistance 2.4 2.6 2.9 k differential internally generated dc bias voltage 2 0.93 1.17 1.38 v differential input voltage swing 632 mv p-p equivalent to 316 mv swing on each leg sysclk pll enabled input capacitance 3 pf single-ended, each pin input resistance 2.4 2.6 2.9 k differential internally generated dc bias voltage 2 0.93 1.17 1.38 v differential input voltage swing 632 mv p-p equivalent to 316 mv swing on each leg crystal resonator with sysclk pll enabled motional resistance 9 100 25 mhz, 3.2 mm 2.5 mm at cut clock output drivers hstl output driver differential output voltage swing 1080 1280 1480 mv output driver static, see figure 27 for output swing vs. frequency common-mode output voltage 2 0.7 0.88 1.06 v cmos output driver output driver static, see figure 28 and figure 29 for output swing vs. frequency output voltage high (v oh ) 2.7 v i oh = 1 ma, pin 37 = 3.3 v output voltage low (v ol ) 0.4 v i ol = 1 ma, pin 37 = 3.3 v output voltage high (v oh ) 1.4 v i oh = 1 ma, pin 37 = 1.8 v output voltage low (v ol ) 0.4 v i ol = 1 ma, pin 37 = 1.8 v total power dissipation dds only 637 765 mw power-on default, except sysclk pll by- passed and cmos driver off; sysclk = 1 ghz; hstl driver off; spur reduction off; f out = 200 mhz dds with spur reduction on 686 823 mw same as dds only case, except both spur reduction channels on dds with hstl driver enabled 657 788 mw same as dds only case, except hstl driver enabled dds with cmos driver enabled 729 875 mw same as dds only case, except cmos driver and s-divider enabled and at 3.3 v; cmos f out = 50 mhz (s-divider = 4) dds with hstl and cmos drivers enabled 747 897 mw same as dds only case, except both hstl and cmos drivers enabled; s-divider enabled and set to 4; cmos f out = 50 mhz dds with sysclk pll enabled 648 777 mw same as dds only case, except 25 mhz on syclk input and pll multiplier = 40 power-down mode 13 16 mw using either the power-down and enable register or the pwrdown pin 1 pin 14 is in the avdd3 group, but it is recommended that pin 14 be tied to pin 1. 2 avss = 0 v.
ad9912 rev. f | page 6 of 40 ac specifications f s = 1 ghz, dac r set = 10 k, unless otherwise noted. power supply pins within the range specified in the dc specifications section. table 2. parameter min typ max unit test conditions/comments fdbk_in input pin 40, pin 41 input frequency range 10 400 mhz minimum differential input level 225 mv p-p ?12 dbm into 50 ; must be ac-coupled 40 v/s system clock input pin 27, pin 28 sysclk pll bypassed input frequency range 250 1000 mhz maximum f out is 0.4 f sysclk duty cycle 45 55 % minimum differential input level 632 mv p-p equivalent to 316 mv swing on each leg sysclk pll enabled vco frequency range, low band 700 810 mhz when in the range, use the low vco band exclusively vco frequency range, auto band 810 900 mhz wh en in the range, use the vco auto band select vco frequency range, high band 900 1000 mhz when in the range, use the high vco band exclusively maximum input rate of system clock pfd 200 mhz without sysclk pll doubler input frequency range 11 200 mhz multiplication range 4 66 integer multiples of 2, maximum pfd rate and system clock frequency must be met minimum differential input level 632 mv p-p equivalent to 316 mv swing on each leg with sysclk pll doubler input frequency range 6 100 mhz multiplication range 8 132 integer multiples of 8 input duty cycle 50 % deviating from 50% duty cycle may adversely affect spurious performance minimum differential input level 632 mv p-p equivalent to 316 mv swing on each leg crystal resonator with sysclk pll enabled crystal resonator frequency range 10 50 mhz at cut, fundamental mode resonator maximum crystal motional resistance 100 see the sysclk inputs section for recommendations clock drivers hstl output driver frequency range 20 725 mhz see figure 27 for maximum toggle rate duty cycle 48 52 % rise time/fall time (20% to 80%) 115 165 ps 100 termination across out/outb, 2 pf load jitter (12 khz to 20 mhz) 1.5 ps f out = 155.52 mhz, 50 mhz system clock input (see figure 12 through figure 14 for test conditions) hstl output driver with 2 multiplier frequency range 400 725 mhz duty cycle 45 55 % rise time/fall time (20% to 80%) 115 165 ps 100 termination across out/outb, 2 pf load subharmonic spur level ?35 dbc without correction jitter (12 khz to 20 mhz) 1.6 ps f out = 622.08 mhz, 50 mhz system clock input (see figure 15 for test conditions) cmos output driver (avdd3/pin 37) @ 3.3 v frequency range 0.008 150 mhz see figure 29 for maximum toggle rate; the s-divider should be used for low frequencies because the fdbk_in minimum frequency is 10 mhz duty cycle 45 55 65 % with 20 pf load and up to 150 mhz rise time/fall time (20% to 80% ) 3 4.6 ns with 20 pf load
ad9912 rev. f | page 7 of 40 parameter min typ max unit test conditions/comments cmos output driver (avdd3/pin 37) @ 1.8 v frequency range 0.008 40 mhz see figure 28 for maximum toggle rate duty cycle 45 55 65 % with 20 pf load and up to 40 mhz rise time/fall time (20% to 80% ) 5 6.8 ns with 20 pf load dac output characteristics dco frequency range (1 st nyquist zone) 0 450 mhz dac lower limit is 0 hz; however, the minimum slew rate for fdbk_in dictates the lower limit if using cmos or hstl outputs output resistance 50 single-ended (e ach pin internally terminated to avss) output capacitance 5 pf full-scale output current 20 31.7 ma range depends on dac r set resistor gain error ?10 +10 % fs output offset 0.6 a voltage compliance range avss ? 0.50 +0.5 avss + 0.50 v outputs connected to a transformer whose center tap is grounded wideband sfdr see the typical performance characteristics section 20.1 mhz output ?79 dbc 0 mhz to 500 mhz 98.6 mhz output ?67 dbc 0 mhz to 500 mhz 201.1 mhz output ?61 dbc 0 mhz to 500 mhz 398.7 mhz output ?59 dbc 0 mhz to 500 mhz narrow-band sfdr see the typical performance characteristics section 20.1 mhz output ?95 dbc 250 khz 98.6 mhz output ?96 dbc 250 khz 201.1 mhz output ?91 dbc 250 khz 398.7 mhz output ?86 dbc 250 khz digital timing specifications time required to enter power-down 15 s time required to leave power-down 18 s reset assert to high-z time for s1 to s4 configuration pins 60 ns time from rising edge of reset to high-z on the s1, s2, s3, s4 configuration pins serial port timing specifications sclk clock rate (1/t clk ) 25 50 mhz refer to figure 56 for all write-related serial port parameters; maximum sclk rate for readback is governed by t dv sclk pulse width high, t high 8 ns sclk pulse width low, t low 8 ns sdo/sdio to sclk setup time, t ds 1.93 ns sdo/sdio to sclk hold time, t dh 1.9 ns sclk falling edge to valid data on sdio/sdo, t dv 11 ns refer to figure 54 csb to sclk setup time, t s 1.34 ns csb to sclk hold time, t h ?0.4 ns csb minimum pulse width high, t pwh 3 ns io_update pin setup time (from sclk rising edge of the final bit) t clk sec t clk = period of sclk in hz io_update pin hold time t clk sec t clk = period of sclk in hz propagation delay fdbk_in to hstl output driver 2.8 ns fdbk_in to hstl output driver with 2 frequency multiplier enabled 7.3 ns fdbk_in to cmos output driver 8.0 ns s-divider bypassed fdbk_in through s-divider to cmos output driver 8.6 ns frequency tuning word update: io_update pin rising edge to dac output 60/f s ns f s = system clock frequency in ghz
ad9912 rev. f | page 8 of 40 absolute maximum ratings table 3. parameter rating analog supply voltage (avdd) 2 v digital supply voltage (dvdd) 2 v digital i/o supply voltage (dvdd_i/o) 3.6 v dac supply voltage (avdd3 pins) 3.6 v maximum digital input voltage ?0.5 v to dvdd_i/o + 0.5 v storage temperature ?65c to +150c operating temperature range ?40c to +85c lead temperature (soldering, 10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 4. thermal resistance package type ja jb jc unit 64-lead lfcsp 25.2 13.9 1.7 c/w typical note that the exposed pad on the bottom of package must be soldered to ground to achieve the specified thermal performance. see the typical performance characteristics section for more information. esd caution
ad9912 rev. f | page 9 of 40 pin configuration and fu nction descriptions pin 1 indicator 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 nc nc avdd nc nc nc avdd avdd avdd avdd sysclk sysclkb avdd avdd loop_filter clkmodesel 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 sclk sdio sdo csb io_update reset pwrdown dvss dvss s4 s3 avdd avss dac_outb dac_out avdd3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dvdd_i/o dvss dvdd dvss dvdd dvss dvdd dvss s1 s2 avdd nc nc avdd3 nc nc notes 1. nc = no connect. 2. the exposed pad must be connected to ground for proper operation. dac_rset avdd3 avdd3 avdd avdd avss avdd fdbk_in fdbk_inb avss out_cmos avdd3 avdd out outb avss 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 06763-002 ad9912 top view (not to scale) figure 2. pin configuration table 5. pin function descriptions pin no. input/ output pin type mnemonic description 1 i power dvdd_i/o i/o digital supply. 2, 4, 6, 8 i power dvss digital ground. connect to ground. 3, 5, 7 i power dvdd digital supply. 9, 10, 54, 55 i/o 3.3 v cmos s1, s2, s3, s4 start-up configuration pins. these pins are configured under program control and do not have internal pull-up/pull-down resistors. 11, 19, 23 to 26, 29, 30, 36, 42, 44, 45, 53 i power avdd analog supply. connect to a nominal 1.8 v supply. 12, 13, 15, 16, 17, 18, 20, 21, 22 nc no connect. these unused pins can be left unconnected. 14, 46, 47, 49 i power avdd3 analog supply. connect to a nominal 3.3 v supply. 27 i differential input sysclk system clock input. the system clock input has internal dc biasing and should always be ac-coupled, except when using a crystal. single-ended 1.8 v cmos can also be used, but it ma y introduce a spur caused by an input duty cycle that is not 50%. when using a crystal, tie the clkmodesel pin to avss, and connect crystal directly to this pin and pin 28. 28 i differential input sysclkb complementary system clock. complementary signal to the input provided on pin 27. use a 0.01 f capacitor to ground on this pin if the signal provided on pin 27 is single-ended. 31 o loop_filter system clock multiplier loop filter. wh en using the frequency multiplier to drive the system clock, an external loop filter must be constructed and attached to this pin. this pin should be pulled down to ground with 1 k resistor when the system clock pll is bypassed. see figure 46 for a diagram of the system clock pll loop filter.
ad9912 rev. f | page 10 of 40 pin no. input/ output pin type mnemonic description 32 i 1.8 v cmos clkmodesel clock mode select. set to gnd when connecting a crystal to the system clock input (pin 27 and pin 28). pull up to 1.8 v when using either an oscillator or an external clock source. this pin can be left unconnected when the system clock pll is bypassed. (see the sysclk inputs section for details on the use of this pin.) 33, 39, 43, 52 o gnd avss analog ground. connect to ground. 34 o 1.8 v hstl outb complementary hstl output. see the specifications and primary 1.8 v differential hstl driver sections for details. 35 o 1.8 v hstl out hstl output. see the specifications and primary 1.8 v differential hstl driver sections for details. 37 i power avdd3 analog supply for cmos output driver . this pin is normally 3.3 v but can be 1.8 v. this pin should be powered even if the cmos driver is not used. see the power supply partitioning section for power supply partitioning. 38 o 3.3 v cmos out_cmos cmos output. see the specifications section and the output clock drivers and 2 frequency multiplier section. this pin is 1.8 v cmos if pin 37 is set to 1.8 v. 40 i differential input fdbk_inb complementary feedback input. when using the hstl and cmos outputs, this pin is connected to the filter ed dac_outb output. this internally biased input is typically ac-coupled, and when configured as such, can accept any differential signal whose single-ended swing is at least 400 mv. 41 i differential input fdbk_in feedback input. in standard operating mode, this pin is connected to the filtered dac_out output. 48 o current set resistor dac_rset dac output current setting resistor. connect a resistor (usually 10 k) from this pin to gnd. see the digital-to-analog (dac) output section. 50 o differential output dac_out dac output. this signal should be filtered and sent back on-chip through the fdbk_in input. this pin has an internal 50 pull-down resistor. 51 o differential output dac_outb complementary dac output. this signal should be filtered and sent back on-chip through the fdbk_inb input. this pin has an internal 50 pull- down resistor. 56, 57 power dvss digital ground. connect to ground. 58 i 3.3 v cmos pwrdown power-down. when this active high pin is asserted, the device becomes inactive and enters the full power-down state. this pin has an internal 50 k pull-down resistor. 59 i 3.3 v cmos reset chip reset. when this active high pin is asserted, the chip goes into reset. note that on power-up, a 10 s reset pulse is internally generated when the power supplies reach a threshold and stabilize. this pin should be grounded with a 10 k resistor if not used. 60 i 3.3 v cmos io_update i/o update. a logic transition from 0 to 1 on this pin transfers data from the i/o port registers to the control registers (see the write section). this pin has an internal 50 k pull-down resistor. 61 i 3.3 v cmos csb chip select. active low. when programming a device, this pin must be held low. in systems where more than one ad9912 is present, this pin enables individual programming of each ad9912. this pin has an internal 100 k pull-up resistor. 62 o 3.3 v cmos sdo serial data output. when th e device is in 3-wire mode, data is read on this pin. there is no internal pull-up/pull-down resistor on this pin. 63 i/o 3.3 v cmos sdio serial data input/output. when the device is in 3-wire mode, data is written via this pin. in 2-wire mode, data reads and writes both occur on this pin. there is no internal pull-up/pull-down resistor on this pin. 64 i 3.3 v cmos sclk serial programming clock. data clock for serial programming. this pin has an internal 50 k pull-down resistor. exposed die pad o gnd epad analog ground. the exposed die pad on the bottom of the package provides the analog ground for th e part; this exposed pad must be connected to ground for proper operation.
ad9912 rev. f | page 11 of 40 typical performance characteristics avdd, avdd3, and dvdd at nominal supply voltage; dac r set = 10 k, unless otherwise noted. see figure 26 for 1 ghz reference phase noise used for generating these plots. 06763-003 0 100 200 300 400 500 output frequency (mhz) ? 50 ?55 ?60 ?65 ?70 ?75 ?80 sfdr (dbc) +25c ?40c +85c 06763-006 0 100 200 300 400 500 frequency (mhz) 10 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 signal power (dbm) 98.6mhz ?67dbc 500mhz 3khz 10khz carrier: sfdr: freq. span: resolution bw: video bw: figure 3. wideband sfdr vs. output frequency at ?40c, +25c, and +85c, sysclk = 1 ghz (sysclk pll bypassed) figure 6. wideband sfdr at 98.6 mhz, sysclk = 1 ghz (sysclk pll bypassed) 06763-004 0 100 200 300 400 500 output frequency (mhz) ? 50 ?55 ?60 ?65 ?70 ?75 ?80 sfdr (dbc) high v dd normal v dd low v dd 06763-007 0 100 200 300 400 500 frequency (mhz) 10 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 signal power (dbm) 201.1mhz ?61dbc 500mhz 3khz 10khz carrier: sfdr: freq. span: resolution bw: video bw: figure 4. variation of wideband sfdr vs. frequency over dac power supply voltage, sysclk = 1 ghz (sysclk pll bypassed) figure 7. wideband sfdr at 201.1 mhz, sysclk = 1 ghz (sysclk pll bypassed) 06763-005 0 100 200 300 400 500 frequency (mhz) 10 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 signal power (dbm) 20.1mhz ?79dbc 500mhz 3khz 10khz carrier: sfdr: freq. span: resolution bw: video bw: 06763-008 0 100 200 300 400 500 frequency (mhz) 10 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 signal power (dbm) 398.7mhz ?59dbc 500mhz 3khz 10khz carrier: sfdr: freq. span: resolution bw: video bw: figure 5. wideband sfdr at 20.1 mhz, sysclk = 1 ghz (sysclk pll bypassed) figure 8. wideband sfdr at 398.7 mhz, sysclk = 1 ghz (sysclk pll bypassed)
ad9912 rev. f | page 12 of 40 06763-009 19.85 19.95 20.05 20.15 20.25 20.35 frequency (mhz) 10 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 signal power (dbm) 20.1mhz ?95dbc 500khz 300hz 1khz carrier: sfdr: freq. span: resolution bw: video bw: figure 9. narrow-band sfdr at 20.1 mhz, sysclk = 1 ghz (sysclk pll bypassed) 06763-010 200.85 200.95 201.05 201.15 201.25 201.35 frequency (mhz) 10 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 signal power (dbm) 201.1mhz ?91dbc 500khz 300hz 1khz carrier: sfdr: freq. span: resolution bw: video bw: figure 10. narrow-band sfdr at 201.1 mhz, sysclk = 1 ghz wenzel oscillator (sysclk pll bypassed) 06763-011 398.45 398.55 398.65 398.75 398.85 398.95 frequency (mhz) 10 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 signal power (dbm) 398.7mhz ?86dbc 500khz 300hz 1khz carrier: sfdr: freq. span: resolution bw: video bw: figure 11. narrow-band sfdr at 398.7 mhz, sysclk = 1 ghz wenzel oscillator (sysclk pll bypassed) 06763-012 100 1k 10k 100k 1m 10m 100m frequency offset (hz) ? 80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 phase noise (dbc/hz) 399mhz 99mhz rms jitter (100hz to 40mhz): 99mhz: 399mhz: 413fs 222fs figure 12. absolute phase noise using hstl driver, sysclk = 1 ghz wenzel oscillator (sysclk pll bypassed) 06763-013 10 100 1k 10k 100k 1m 10m 100m frequency offset (hz) ? 80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 phase noise (dbc/hz) 399mhz 99mhz rms jitter (12khz to 20mhz): 99mhz: 399mhz: 0.98ps 0.99ps figure 13. absolute phase noise using hstl driver, sysclk = 1 ghz (sysclk pll driven by rohde & schwarz sma100 signal generator at 83.33 mhz ) 06763-014 10 100 1k 10k 100k 1m 10m 100m frequency offset (hz) ? 80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 phase noise (dbc/hz) 399mhz 99mhz rms jitter (12khz to 20mhz): 99mhz: 399mhz: 1.41ps 1.46ps figure 14. absolute phase noise using hstl driver, sysclk = 1 ghz (sysclk pll driven by rohde & schwarz sma100 signal generator at 25 mhz )
ad9912 rev. f | page 13 of 40 06763-015 100 1k 10k 100k 1m 10m 100m frequency offset (hz) ? 100 ?110 ?120 ?130 ?140 ?150 phase noise (dbc/hz) 800mhz 600mhz rms jitter (100hz to 100mhz): 600mhz: 800mhz: 585fs 406fs figure 15. absolute phase noise using hstl driver, sysclk = 1 ghz wenzel oscillator (sysclk pll bypassed), hstl output doubler enabled 06763-016 100 1k 10k 100k 1m 10m 100m frequency offset (hz) ? 110 ?120 ?130 ?140 ?150 ?160 phase noise (dbc/hz) 150mhz 50mhz 10mhz rms jitter (100hz to 20mhz): 150mhz: 50mhz: 308fs 737fs figure 16. absolute phase noise using cmos driver at 3.3 v, sysclk = 1 ghz wenzel oscillator (sysclk pll bypassed) dds run at 200 msps for 10 mhz plot 06763-017 100 1k 10k 100k 1m 10m 100m frequency offset (hz) ? 110 ?120 ?130 ?140 ?150 ?160 phase noise (dbc/hz) 50mhz 10mhz rms jitter (100hz to 20mhz): 50mhz: 790fs figure 17. absolute phase noise using cmos driver at 1.8 v, sysclk = 1 ghz wenzel oscillator (sysclk pll bypassed) 06763-018 250 375 500 625 750 875 1000 system clock frequency (mhz) 800 700 600 500 400 300 200 100 0 power dissipation (mw) total 3.3v 1.8v figure 18. power dissipation vs. system clock frequency (sysclk pll bypassed), f out = f sysclk /5, hstl driver on, cmos driver on, spurkiller off 06763-019 0 100 200 300 400 output frequency (mhz) 800 700 600 500 400 300 200 100 0 power dissipation (mw) total 3.3v 1.8v figure 19. power dissipation vs. output frequency sysclk = 1 ghz (sysclk pll bypassed), hstl driver on, cmos driver on, spurkiller off 06763-020 0 100 200 300 400 500 frequency (mhz) ?20 ?30 ?40 10 0 ?10 ?50 ?60 ?70 ?80 ?90 ?100 signal power (dbm) carrier: sfdr w/o spurkiller: sfdr with spurkiller: frequency span: resolution bw: video bw: 399mhz ?63.7dbc ?69.3dbc 500mhz 3khz 30khz these two spurs eliminated with spurkiller figure 20. sfdr comparison with and without spurkiller, sysclk = 1 ghz, f out = 400 mhz
ad9912 rev. f | page 14 of 40 06763-051 100 1k 10k 100k 1m 10m 100m frequency offset (hz) ?125 ? 115 ?135 ?145 ?155 ?165 ?175 phase noise (dbc/hz) rms jitter (100hz to 20mhz): 50mhz: 200mhz: 400mhz: 62fs 37fs 31fs 200mhz 400mhz 50mhz figure 21. absolute phase noise of unfiltered dac output, f out = 50 mhz, 200 mhz, and 400 mhz, sysclk driven by a 1 ghz wenzel oscillator (sysclk pll bypassed) 06763-052 100 1k 10k 100k 1m 10m 100m frequency offset (hz) ?125 ? 115 ?135 ?145 ?155 ?165 ?175 phase noise (dbc/hz) rms jitter (100hz to 20mhz): 69fs figure 22. absolute phase noise of unfiltered dac output, f out = 63 mhz, sysclk driven by a 1 ghz wenzel oscillator (sysclk pll bypassed) 06763-053 100 1k 10k 100k 1m 10m 100m frequency offset (hz) ?125 ? 115 ?135 ?145 ?155 ?165 ?175 phase noise (dbc/hz) rms jitter (100hz to 40mhz): 61fs figure 23. absolute phase noise of unfiltered dac output, f out = 171 mhz, sysclk driven by a 1 ghz wenzel oscillator (sysclk pll bypassed) 06763-054 100 1k 10k 100k 1m 10m 100m frequency offset (hz) ?125 ? 115 ?135 ?145 ?155 ?165 ?175 phase noise (dbc/hz) rms jitter (100hz to 100mhz): 83fs figure 24. absolute phase noise of unfiltered dac output, f out = 258.3 mhz, sysclk driven by a 1 ghz wenzel oscillator (sysclk pll bypassed) 06763-055 100 1k 10k 100k 1m 10m 100m frequency offset (hz) ?125 ? 115 ?135 ?145 ?155 ?165 ?175 phase noise (dbc/hz) rms jitter (100hz to 100mhz): 82fs figure 25. absolute phase noise of unfiltered dac output, f out = 311.6 mhz, sysclk driven by a 1 ghz wenzel oscillator (sysclk pll bypassed) 06763-056 100 1k 10k 100k 1m 10m 100m frequency offset (hz) ?120 ? 110 ?130 ?140 ?150 ?160 ?170 phase noise (dbc/hz) rms jitter (100hz to 100mhz): 22fs figure 26. absolute phase noise of 1 ghz reference used for performance plots; wenzel components used: 100 mhz oscillator, lnba-13-24 amp, lnom 100-5 multiplier, lndd 500-14 diode doubler
ad9912 rev. f | page 15 of 40 06763-021 0 200 400 600 800 frequency (mhz) 650 600 550 500 450 amplitude (mv) nom skew 25c, 1.8v supply worst case (slow skew 90c, 1.7v supply) 06763-024 0 0.5 1.0 1.5 2.0 2.5 time (ns) 0.4 0.6 0.2 0 ?0.2 ?0.4 ?0.6 amplitude (v) frequency = 600mhz t rise (20% 80%) = 104ps t fall (80% 20%) = 107ps v p-p = 1.17v diff. duty cycle = 50% figure 27. hstl output driver single-ended peak-to-peak amplitude vs. toggle rate (100 across differential pair) figure 30. typical hstl output waveform, nominal conditions, dc-coupled, differential probe across 100 load 06763-022 0 1 02 03 04 frequency (mhz) 2.5 2.0 1.5 1.0 0.5 0 amplitude (v) 06763-025 0 20 40 60 80 100 time (ns) 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 ?0.2 amplitude (v) frequency = 20mhz t rise (20% 80%) = 5.5ns t fall (80% 20%) = 5.9ns v p-p = 1.8v duty cycle = 53% 0 nom skew 25c, 1.8v supply (20pf) worst case (slow skew 90c, 1.7v supply (20pf)) figure 31. typical cmos output driver waveform (@ 1.8 v), nominal conditions, estimated capacitance = 5 pf figure 28. cmos output driver peak-to-peak amplitude vs. toggle rate (avdd3 = 1.8 v) with 20 pf load 06763-023 0 50 100 150 frequency (mhz) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 amplitude (v) nom skew 25c, 1.8v supply (20pf) worst case (slow skew 90c, 3.0v supply (20pf)) 06763-026 0 102030405 time (ns) 3.3 2.8 2.3 1.8 1.3 0.8 0.3 ?0.2 0 amplitude (v) frequency = 40mhz t rise (20% 80%) = 2.25ns t fall (80% 20%) = 2.6ns v p-p = 3.3v duty cycle = 52% figure 32. cmos output driv er waveform (@ 3.3 v), nominal conditions, estimated capacitance = 5 pf figure 29. cmos output driver peak-to-peak amplitude vs. toggle rate (avdd3 = 3.3 v) with 20 pf load
ad9912 rev. f | page 16 of 40 input/output termination recommendations downstream device (high-z) ad9912 1.8v hstl output 100 ? 06763-027 0.01f 0.01f figure 33. ac-coupled hstl output driver downstream device (high-z) ad9912 1.8v hstl output 50? 50? 06763-028 avdd/2 figure 34. dc-coupled hstl output driver ad9912 self-biasing sysclk input (crystal mode) 10pf* 06763-029 10pf* refer to crystal data sheet. * figure 35. sysclk input, xtal ad9912 self-biasing sysclk input 0.1f 0.1f 100? 06763-030 clock source with diff. output figure 36. sysclk differential input, non-xtal ad9912 self-biasing sysclk input 0.01f 0.01f 06763-049 clock source with single-ended 1.8v cmos output figure 37. sysclk single-ended input, non-xtal ad9912 self-biasing fdbk input 0.1f 0.1f 06763-050 100? (optional) figure 38. fdbk_in input
ad9912 rev. f | page 17 of 40 theory of operation 06763-031 dds/dac frequency tuning word s 2 digital synthesis core control logic low noise clock multiplier amp sysclk port external analog low-pass filter external loop filter digital interface sysclk sysclkb s1 to s4 fdbk_in fdbk_inb dac_out dac_outb out outb out_cmos configuration logic figure 39. detailed block diagram overview the ad9912 is a high performance, low noise, 14-bit dds clock synthesizer with integrated comparators for applications desiring an agile, finely tuned square or sinusoidal output signal. a digitally controlled oscillator (dco) is implemented using a direct digital synthesizer (dds) with an integrated output dac, clocked by the system clock. a bypassable pll-based frequency multiplier is present, enabling use of an inexpensive, low frequency source for the system clock. for best jitter performance, the system clock pll should be bypassed, and a low noise, high frequency system clock should be provided directly. sampling theory sets an upper bound for the dds output frequency at 50% of f s (where f s is the dac sample rate), but a practical limitation of 40% of f s is generally recommended to allow for the selectivity of the required off-chip reconstruction filter. the output signal from the reconstruction filter can be fed back to the ad9912 to be processed through the output circuitry. the output circuitry includes hstl and cmos output buffers, as well as a frequency doubler for applications that need frequencies above the nyquist level of the dds. the ad9912 also offers preprogrammed frequency profiles that allow the user to generate frequencies without programming the part. the individual functional blocks are described in the following sections. direct digital synthesizer (dds) the frequency of the sinusoid generated by the dds is determined by a frequency tuning word (ftw), which is a digital (that is, numeric) value. unlike an analog sinusoidal generator, a dds uses digital building blocks and operates as a sampled system. thus, it requires a sampling clock (f s ) that serves as the fundamental timing source of the dds. the accumulator behaves as a modulo-2 48 counter with a program- mable step size that is determined by the frequency tuning word (ftw). a block diagram of the dds is shown in figure 40 .
ad9912 rev. f | page 18 of 40 06763-032 dac (14-bit) angle to amplitude conversion 14 19 19 48 48 48 14 phase offset qd 48-bit accumulator frequency tuning word (ftw) f s dac_rset dac_out dac_outb dac i-set registers and logic figure 40. dds block diagram the input to the dds is a 48-bit ftw that provides the accu- mulator with a seed value. on each cycle of f s , the accumulator adds the value of the ftw to the running total of its output. for example, given an ftw = 5, the accumulator increments the count by 5 sec on each f s cycle. over time, the accumulator reaches the upper end of its capacity (2 48 in this case) and then rolls over, retaining the excess. the average rate at which the accumulator rolls over establishes the frequency of the output sinusoid. the following equation defines the average rollover rate of the accumulator and establishes the output frequency (f dds ) of the dds: s dds f ftw f ? ? ? ? ? ? = 48 2 solving this equation for ftw yields ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = s dds f f ftw 48 2round for example, given that f s = 1 ghz and f dds = 19.44 mhz, then ftw = 5,471,873,547,255 (0x04fa05143bf7). the relative phase of the sinusoid can be controlled numerically, as well. this is accomplished using the phase offset function of the dds (a programmable 14-bit value (phase); see the i/o register map section). the resulting phase offset, ? (radians), is given by ? ? ? ? ? ? = 14 2 2 phase digital-to-analog (dac) output the output of the digital core of the dds is a time series of numbers representing a sinusoidal waveform. this series is translated to an analog signal by means of a digital-to-analog converter (dac). the dac outputs its signal to two pins driven by a balanced current source architecture (see the dac output diagram in figure 41 ). the peak output current derives from a combination of two factors. the first is a reference current (i dac_ref ) that is established at the dac_rset pin, and the second is a scale factor that is programmed into the i/o register map. the value of i dac_ref is set by connecting a resistor (r dac_ref ) between the dac_rset pin and ground. the dac_rset pin is internally connected to a virtual voltage reference of 1.2 v nominal, so the reference current can be calculated by ref dac refdac r i _ _ 2.1 = note that the recommended value of i dac_ref is 120 a, which leads to a recommended value for r dac_ref of 10 k. the scale factor consists of a 10-bit binary number (fsc) programmed into the dac full-scale current register in the i/o register map. the full-scale dac output current (i dac_fs ) is given by ? ? ? ? ? ? + = 1024 192 72 _ _ fsc ii refdac fsdac using the recommended value of r dac_ref , the full-scale dac output current can be set with 10-bit granularity over a range of approximately 8.6 ma to 31.7 ma. 20 ma is the default value. 06763-033 switch control code i fs /2 i fs /2 a vdd3 avss current switch array current switch array dac_out dac_outb internal 50? internal 50? i fs /2 + i code i fs /2 ? i code i fs 49 51 50 52 figure 41. dac output reconstruction filter the origin of the output clock signal produced by the ad9912 is the combined dds and dac. the dac output signal appears as a sinusoid sampled at f s . the frequency of the sinusoid is determined by the frequency tuning word (ftw) that appears at the input to the dds. the dac output is typically passed through an external reconstruction filter that serves to remove the artifacts of the sampling process and other spurs outside the filter bandwidth. if desired, the signal can then be brought back on-chip to be converted to a square wave that is routed internally to the output clock driver or the 2 dll multiplier.
ad9912 rev. f | page 19 of 40 primary signal filter response sin(x)/x envelope spurs image 0 image 1 image 2 image 3 image 4 0 ?20 ?40 ?60 ?80 ?100 magnitude (db) f s /2 f s 3 f s /2 2 f s 5 f s /2 f base band 06763-034 figure 42. dac spectrum vs. re construction filter response because the dac constitutes a sampled system, its output must be filtered so that the analog waveform accurately represents the digital samples supplied to the dac input. the unfiltered dac output contains the (typically) desired baseband signal, which extends from dc to the nyquist frequency (f s /2). it also contains images of the baseband signal that theoretically extend to infinity. notice that the odd images (shown in figure 42 ) are mirror images of the baseband signal. furthermore, the entire dac output spectrum is affected by a sin(x)/x response, which is caused by the sample-and-hold nature of the dac output signal. for applications using the fundamental frequency of the dac output, the response of the reconstruction filter should preserve the baseband signal (image 0), while completely rejecting all other images. however, a practical filter implementation typically exhibits a relatively flat pass band that covers the desired output frequency plus 20%, rolls off as steeply as possible, and then maintains significant (though not complete) rejection of the remaining images. depending on how close unwanted spurs are to the desired signal, a third-, fifth-, or seventh-order elliptic low-pass filter is common. some applications operate off an image above the nyquist frequency, and those applications use a band-pass filter instead of a low-pass filter. the design of the reconstruction filter has a significant impact on the overall signal performance. therefore, good filter design and implementation techniques are important for obtaining the best possible jitter results. fdbk_in inputs the fdbk_in pins serve as the input to the comparators and output drivers of the ad9912. typically, these pins are used to receive the signal generated by the dds after it has been band- limited by the external reconstruction filter. a diagram of the fdbk_in input pins is provided in figure 43 , which includes some of the internal components used to bias the input circuitry. note that the fdbk_in input pins are internally biased to a dc level of ~1 v. care should be taken to ensure that any external connections do not disturb the dc bias because this may significantly degrade performance. 06763-035 15k? 15k? ~1pf ~1pf to s-divider and clock output section avss ~1v avss ~2pf + fdbk_in fdbk_inb figure 43. differential fdbk_in inputs
ad9912 rev. f | page 20 of 40 sysclk inputs functional description a n external time base connects to the ad9912 at the sysclk pins to generate the internal high frequency system clock (f s ). t he sysclk inputs can be operated in one of the following three modes: ? sysclk pll bypassed ? sysclk pll enabled with input signal generated externally ? crystal resonator with sysclk pll enabled a functional diagram of the system clock generator is shown in figure 44 . t he sysclk pll multiplier path is enabled by a logic 0 (default) in the pd sysclk pll bit (register 0x0010, bit 4) of the i/o register map. the sysclk pll multiplier can be driven from the sysclk input pins by one of two means, depending on the logic level applied to the 1.8 v cmos clkmodesel pin. when clkmodesel = 0, a crystal can be connected directly across the sysclk pins. when clkmodesel = 1, the maintaining amp is disabled, and an external frequency source (such as an oscillator or signal generator) can be connected directly to the sysclk input pins. note that clkmodesel = 1 does not disable the system clock pll. t he maintaining amp on the ad9912 sysclk pins is intended for 25 mhz, 3.2 mm 2.5 mm at cut fundamental mode crystals with a maximum motional resistance of 100 . the following crystals, listed in alphabetical or der, meet these criteria (as of the revision date of this data sheet): ? avx/kyocera cx3225sb ? ecs ecx-32 ? epson/toyocom tsx-3225 ? fox fx3225bs ? ndk nx3225sa note that although these crystals meet the preceding criteria according to their data sheets, analog devices, inc., does not guarantee their operation with the ad9912, nor does analog devices endorse one supplier of crystals over another. when the sysclk pll multiplier path is disabled, the ad9912 must be driven by a high frequency signal source (250 mhz to 1 ghz). the signal thus applied to the sysclk input pins becomes the internal dac sampling clock (f s ) after passing through an internal buffer. it is important to note that when bypassing the system clock pll, the loop_filter pin (pin 31) should be pulled down to the analog ground with a 1 k resistor. sysclk pll doubler the sysclk pll multiplier path offers an optional sysclk pll doubler. this block comes before the sysclk pll multiplier and acts as a frequency doubler by generating a pulse on each edge of the sysclk input signal. the sysclk pll multiplier locks to the falling edges of this regenerated signal. the impetus for doubling the frequency at the input of the sysclk pll multiplier is that an improvement in overall phase noise performance can be realized. the main drawback is that the doubler output is not a rectangular pulse with a constant duty cycle even for a perfectly symmetric sysclk input signal. this results in a subharmonic appearing at the same frequency as the sysclk input signal, and the magnitude of the subharmonic can be quite large. when employing the doubler, care must be taken to ensure that the loop bandwidth of the sysclk pll multiplier adequately suppresses the subharmonic. the benefit offered by the doubler depends on the magnitude of the subharmonic, the loop bandwidth of the sysclk pll multiplier, and the overall phase noise requirements of the specific application. in many applications, the ad9912 clock output is applied to the input of another pll, and the subhar- monic is often suppressed by the relatively narrow bandwidth of the downstream pll. note that generally, the benefits of the sysclk pll doubler are realized for sysclk input frequencies of 25 mhz and above. 06763-036 1 0 1 0 1 0 bipolar edge detector 2 2 with crystal resonator 2 2 1 0 2 2 2 sysclk pll enabled with external drive sysclk pll bypassed sysclk pll multiplier 1 0 bipolar edge detector (i/o register bit) pd sysclk pll (i/o register bit) dac sample clock loop_filter sysclk sysclkb clkmodesel 2 figure 44. system clock generator block diagram
ad9912 rev. f | page 21 of 40 sysclk pll multiplier when the sysclk pll multiplier path is employed, the frequency applied to the sysclk input pins must be limited so as not to exceed the maximum input frequency of the sysclk pll phase detector. a block diagram of the sysclk generator appears in figure 45 . 06763-037 phase frequency detector charge pump vco 2 n ~2pf (n = 2 to 33) k vco (high/low range) 2 i cp (125a, 250a, 375a) sysclk pll multiplier loop_filter from s ysclk input dac sample clock 1ghz figure 45. block diagram of the sysclk pll the sysclk pll multiplier has a 1 ghz vco at its core. a phase/frequency detector (pfd) and charge pump provide the steering signal to the vco in typical pll fashion. the pfd operates on the falling edge transitions of the input signal, which means that the loop locks on the negative edges of the reference signal. the charge pump gain is controlled via the i/o register map by selecting one of three possible constant current sources ranging from 125 a to 375 a in 125 a steps. the center frequency of the vco is also adjustable via the i/o register map and provides high/low gain selection. the feedback path from vco to pfd consists of a fixed divide-by-2 prescaler followed by a programmable divide-by-n block, where 2 n 33. this limits the overall divider range to any even integer from 4 to 66, inclusive. the value of n is programmed via the i/o register map via a 5-bit word that spans a range of 0 to 31, but the internal logic automatically adds a bias of 2 to the value entered, extending the range to 33. care should be taken when choosing these values so as not to exceed the maximum input frequency of the sysclk pll phase detector or sysclk pll doubler. these values can be found in the ac specifications section. external loop filter (sysclk pll) the loop bandwidth of the sysclk pll multiplier can be adjusted by means of three external components as shown in figure 46 . the nominal gain of the vco is 800 mhz/v. the recommended component values (shown in table 6 ) establish a loop bandwidth of approximately 1.6 mhz with the charge pump current set to 250 a. the default case is n = 40, and it assumes a 25 mhz sysclk input frequency and generates an internal dac sampling frequency (f s ) of 1 ghz. 06763-038 charge pump ~2pf loop_filter c2 r1 c1 external loop filter vco ad9912 ferrite bead avdd 29 26 31 figure 46. external loop filter for sysclk pll table 6. recommended loop fi lter values for a nominal 1.5 mhz sysclk pll loop bandwidth multiplier r1 series c1 shunt c2 <8 390 1 nf 82 pf 10 470 820 pf 56 pf 20 1 k 390 pf 27 pf 40 (default) 2.2 k 180 pf 10 pf 60 2.7 k 120 pf 5 pf detail of sysclk differential inputs a diagram of the sysclk input pins is provided in figure 47 . included are details of the internal components used to bias the input circuitry. these components have a direct effect on the static levels at the sysclk input pins. this information is intended to aid in determining how best to interface to the device for a given application. 0 6763-039 500? 500? ~1.5pf ~1.5pf internal clock v ss ~1v v ss ~2pf + sysclk pll bypassed 1k? 1k? ~3pf ~3pf internal clock v ss ~1v v ss ~2pf + sysclk pll enabled amp internal clock crystal resonator with sysclk pll enabled mux sysclk s ysclkb figure 47. differential sysclk inputs
ad9912 rev. f | page 22 of 40 note that the sysclk pll bypassed and sysclk pll enabled input paths are internally biased to a dc level of ~1 v. care should be taken to ensure that any external connections do not disturb the dc bias because this may significantly degrade performance. generally, it is recommended that the sysclk inputs be ac-coupled, except when using a crystal resonator. output clock drivers and 2 frequency multiplier there are two output drivers provided by the ad9912. the primary output driver supports differential 1.8 v hstl output levels, while the secondary supports either 1.8 v or 3.3 v cmos levels, depending on whether pin 37 is driven at 1.8 v or 3.3 v. the primary differential driver nominally provides an output voltage with 100 load applied differentially. the source impedance of the driver is approximately 100 for most of the output clock period; during transition between levels, the source impedance reaches a maximum of about 500 . the driver is designed to support output frequencies of up to and beyond the oc-12 network rate of 622.08 mhz. the output clock can also be powered down by a control bit in the i/o register map. primary 1.8 v differential hstl driver the dds produces a sinusoidal clock signal that is sampled at the system clock rate. this dds output signal is routed off chip where it is passed through an analog filter and brought back on chip for buffering and, if necessary, frequency doubling. where possible, for the best jitter performance, it is recommended that the frequency doubler be bypassed. the 1.8 v hstl output should be ac-coupled, with 100 termi- nation at the destination. the driver design has low jitter injection for frequencies in the range of 50 mhz to 750 mhz. refer to the ac specifications section for the exact frequency limits. 2 frequency multiplier the ad9912 can be configured (via the i/o register map) with an internal 2 delay-locked loop (dll) multiplier at the input of the primary clock driver. the extra octave of frequency gain allows the ad9912 to provide output clock frequencies that exceed the range available from the dds alone. these settings are found in register 0x0010 and register 0x0200. the input to the dll consists of the filtered dds output signal after it has been squared up by an integrated clock receiver circuit. the dll can accept input frequencies in the range of 200 mhz to 400 mhz. single-ended cmos output in addition to the high-speed differential output clock driver, the ad9912 provides an independent, single-ended output, cmos clock driver that is very good for frequencies up to 150 mhz. the signal path for the cmos clock driver can either include or bypass the cmos output divider. if the cmos output divider is bypassed, the hstl and cmos drivers are the same frequency as the signal presented at the fdbk_in pins. when using the cmos output in this configu- ration, the dds output frequency should be in the range of 30 mhz to 150 mhz. at low output frequencies (<30 mhz), the low slew rate of the dac results in a higher noise floor. this can be remedied by running the dds at 100 mhz or greater and using the cmos divider. at an output frequency of 50 mhz, the best technique depends on the users application. running the dds at 200 mhz, and using a cmos divider of 4, results in a lower noise floor, but at the expense of close-in phase noise. at frequencies greater than 150 mhz, the hstl output should be used. cmos output divider (s-divider) the cmos output divider is 16 bi ts cascaded with an additional divide-by-two. the divider is therefore capable of integer division from 1 to 65,535 (index of 1) or from 2 to 131,070 (index of 2). the divider is programmed via the i/o register map to trigger on either the rising (default) or falling edge of the feedback signal. the cmos output divider is an integer divider capable of handling frequencies well above the nyquist limit of the dds. the s-divider/2 bit (register 0x0106, bit 0) must be set when fdbk_in is greater than 400 mhz. note that the actual output divider values equal the value stored in the output divider register minus one. therefore, to have an output divider of one, the user writes zeros to the output divider register. harmonic spur reduction the most significant spurious signals produced by the dds are harmonically related to the desired output frequency of the dds. the source of these harmonic spurs can usually be traced to the dac, and the spur level is in the ?60 dbc range. this ratio represents a level that is about 10 bits below the full-scale output of the dac (10 bits down is 2 ?10 , or 1/1024). such a spur can be reduced by combining the original signal with a replica of the spur, but offset in phase by 180. this idea is the foundation of the technique used to reduce harmonic spurs in the ad9912. because the dac has 14-bit resolution, a ?60 dbc spur can be synthesized using only the lower 4 bits of the dac full-scale range. that is, the 4 lsbs can create an output level that is approximately 60 db below the full-scale level of the dac (commensurate with a ?60 dbc spur). this fact gives rise to a means of digitally reducing harmonic spurs or their aliased images in the dac output spectrum by digitally adding a sinusoid at the input of the dac with a similar magnitude as the offending spur, but shifted in phase to produce destructive interference.
ad9912 rev. f | page 23 of 40 th e procedure for tuning the spur reduction is as follows: although the worst spurs tend to be harmonic in origin, the fact that the dac is part of a sampled system results in the possibility of spurs appearing in the output spectrum that are not harmoni- cally related to the fundamental. for example, if the dac is sampled at 1 ghz and generates an output sinusoid of 170 mhz, the fifth harmonic would normally be at 850 mhz. however, because of the sampling process, this spur appears at 150 mhz, only 20 mhz away from the fundamental. therefore, when attempting to reduce dac spurs it is important to know the actual location of the harmonic spur in the dac output spectrum based on the dac sample rate so that its harmonic number can be reduced. 1. determine which offending harmonic spur to reduce and its amplitude. enter that harmonic number into bit 0 to bit 3 of register 0x0500/register 0x0505. 2. turn off the fundamental by setting bit 7 of register 0x0013 and enable the spurkiller channel by setting bit 7 of register 0x0500/register 0x0505. 3. adjust the amplitude of the spurkiller channel so that it matches the amplitude of the offending spur. 4. turn the fundamental on by clearing bit 7 of register 0x0013. 5. adjust the phase of the spurkiller channel so that maximum interference is achieved. the mechanics of performing harmonic spur reduction is shown in figure 48 . it essentially consists of two additional dds cores operating in parallel with the original dds. this enables the user to reduce two different harmonic spurs from the second to the 15 th with nine bits of phase offset control () and eight bits of amplitude control. note that the spurkiller setting is sensitive to the loading of the dac output pins, and that a dds reset is required if a spurkiller channel is turned off. the dds can be reset by setting bit 0 of register 0x0012, and resetting the part is not necessary. the performance improvement offered by this technique varies widely and depends on the conditions used. given this extreme variability, it is impossible to define a meaningful specification to guarantee spurkiller performance. current data indicate that a 6 db to 8 db improvement is possible for a given output frequency using a common setting over process, temperature, and voltage. there are frequencies, however, where a common setting can result in much greater improvement. manually adjusting the spurkiller settings on individual parts can result in more than 30 db of spurious performance improvement. th e dynamic range of the cancellation signal is further aug- mented by a gain bit associated with each channel. when this bit is set, the magnitude of the cancellation signal is doubled by employing a 1-bit left-shift of the data. however, the shift operation reduces the granularity of the cancellation signal magnitude. the full-scale amplitude of a cancellation spur is approximately ?60 dbc when the gain bit is a logic 0 and approximately ?54 dbc when the gain bit is a logic 1. 06763-040 0 1 1 0 14 14 19 19 qd 48 14 dac (14-bit) dac_out dac_outb 4 9 4 9 8 8 shift 1 0 shift headroom correction harmonic spur cancellation ch1 harmonic number ch1 cancellation phase offset ch2 harmonic number ch2 cancellation phase offset ch1 cancellation magnitude ch2 cancellation magnitude ch1 gain ch2 gain spur cancellation enable angle to amplitude conversion dds phase offset 14 48 48-bit accumulator dds 48-bit frequency t urning word (ftw) sysclk 2-channel harmonic frequency generator ch1 ch2 dac_rset dac i-set registers and logic figure 48. spur reduction circuit diagram
ad9912 rev. f | page 24 of 40 thermal performance table 7. thermal parameters symbol thermal characteristic using a jedec51-7 plus jedec51-5 2s2p test board value unit ja junction-to-ambient thermal resistance, 0.0 m/sec air flow per jedec jesd51-2 (still air) 25.2 c/w jma junction-to-ambient thermal resistance, 1.0 m/sec air flow per jedec jesd51-6 (moving air) 22.0 c/w jma junction-to-ambient thermal resistance, 2.0 m/sec air flow per jedec jesd51-6 (moving air) 19.8 c/w jb junction-to-board thermal resistance, 1.0 m/sec ai r flow per jedec jesd51-8 (moving air) 13.9 c/w jc junction-to-case thermal resistance (die-to-h eat sink) per mil-std 883, method 1012.1 1.7 c/w jt junction-to-top-of-package characterization parameter, 0 m/sec air flow per jedec jesd51-2 (still air) 0.1 c/w the ad9912 is specified for a case temperature (t case ). to ensure that t case is not exceeded, an airflow source can be used. use the following equation to determine the junction tempera- ture on the application pcb: t j = t case + ( jt pd ) where: t j is the junction temperature (c). t case is the case temperature (c) measured by customer at top center of package. jt is the value from table 7 . pd is the power dissipation (see the total power dissipation section in the specifications section). va lu e s of ja are provided for package comparison and pcb design considerations. ja can be used for a first-order approximation of t j by the equation t j = t a + ( ja pd ) where t a is the ambient temperature (c). va lu e s of jc are provided for package comparison and pcb design considerations when an external heat sink is required. va lu e s of jb are provided for package comparison and pcb design considerations. the values in table 7 apply to both 64-lead package options.
ad9912 rev. f | page 25 of 40 power-up power-on reset o n initial power-up, the ad9912 internally generates a 75 ns reset pulse. the pulse is initiated when both of the following two conditions are met: ? the 3.3 v supply is greater than 2.35 v 0.1 v. ? the 1.8 v supply is greater than 1.4 v 0.05 v. less than 1 ns after reset goes high, the s1 to s4 configuration pins go high impedance and remain high impedance until reset is deactivated. this allows strapping and configuration during reset. because of this reset sequence, external power supply sequenc- ing is not critical. default output frequency on power-up the four status pins (s1 to s4) are used to define the output frequency of the dds at power-up even though the i/o registers have not yet been programmed. at power-up, internal logic initiates a reset pulse of about 10 ns. during this time, s1 to s4 briefly function as input pins and can be driven externally. any logic levels thus applied are transferred to a 4-bit register on the falling edge of the internally initiated pulse. the same behavior occurs when the reset pin is asserted manually. setting up s1 to s4 for default dds startup is accomplished by connecting a resistor to each pin (either pull-up or pull-down) to produce the desired bit pattern, yielding 16 possible states that are used both to address an internal 8 16 rom and to select the sysclk mode (see table 8 ). the rom contains eight 16-bit dds frequency tuning words (ftws), one of which is selected by the state of the s1 to s3 pins. the selected ftw is transferred to the ftw0 register in the i/o register map without the need for an i/o update. this ensures that the dds generates the selected frequency even if the i/o registers have not been programmed. the state of the s4 pin selects whether the internal system clock is generated by means of the internal sysclk pll multiplier or not (see the sysclk inputs section for details). the dds output frequency listed in table 8 assumes that the internal dac sampling frequency (f s ) is 1 ghz. these frequencies scale 1:1 with f s , meaning that other start-up frequencies are available by varying the sysclk frequency. at startup, the internal frequency multiplier defaults to 40 when the xtal/pll mode is selected via the status pins. table 8. default power-up frequency options for 1 ghz system clock status pin sysclk input mode output frequency (mhz) s4 s3 s2 s1 0 0 0 0 xtal/pll 0 0 0 0 1 xtal/pll 38.87939 0 0 1 0 xtal/pll 51.83411 0 0 1 1 xtal/pll 61.43188 0 1 0 0 xtal/pll 77.75879 0 1 0 1 xtal/pll 92.14783 0 1 1 0 xtal/pll 122.87903 0 1 1 1 xtal/pll 155.51758 1 0 0 0 direct 0 1 0 0 1 direct 38.87939 1 0 1 0 direct 51.83411 1 0 1 1 direct 61.43188 1 1 0 0 direct 77.75879 1 1 0 1 direct 92.14783 1 1 1 0 direct 122.87903 1 1 1 1 direct 155.51758
ad9912 rev. f | page 26 of 40 power supply partitioning the ad9912 features multiple power supplies, and their power consumption varies with its configuration. this section covers which power supplies can be grouped together and how the power consumption of each block varies with frequency. the numbers quoted here are for comparison only. refer to the specifications section for exact numbers. with each group, use bypass capacitors of 1 f in parallel with a 10 f. the recommendations here are for typical applications, and for these applications, there are four groups of power supplies: 3.3 v digital, 3.3 v analog, 1.8 v digital, and 1.8 v analog. applications demanding the highest performance may require additional power supply isolation. important: all power supply pins must receive power regardless of whether that block is used. 3.3 v supplies dvdd_i/o (pin 1) and avdd3 (pin 14) although one of these pins is analog and the other is digital, these two 3.3 v supplies can be grouped together. the power consumption on pin 1 varies dynamically with serial port activity. avdd3 (pin 37) this is the cmos driver supply. it can be either 1.8 v or 3.3 v, and its power consumption is a function of the output frequency and loading of out_cmos (pin 38). if the cmos driver is used at 3.3 v, this supply should be isolated from other 3.3 v supplies with a ferrite bead to avoid a spur at the output frequency. if the hstl driver is not used, avdd3 (pin 37) can be connected (using a ferrite bead) to avdd3 (pin 46, pin 47, and pin 49). if the hstl driver is used, connect avdd3 (pin 37) to pin 1 and pin 14, using a ferrite bead. if the cmos driver is used at 1.8 v, avdd3 (pin 37) can be connected to avdd (pin 36). if the cmos driver is not used, avdd3 (pin 37) can be tied directly to the 1.8 v avdd (pin 36) and the cmos driver powered down using register 0x0010. avdd3 (pin 46, pin 47, and pin 49) these are 3.3 v dac power supplies that typically consume about 25 ma. at a minimum, a ferrite bead should be used to isolate these from other 3.3 v supplies, with a separate regulator being ideal. 1.8 v supplies dvdd (pin 3, pin 5, and pin 7) these pins should be grouped together and isolated from the 1.8 v avdd supplies. for most applications, a ferrite bead provides sufficient isolation, but a separate regulator may be necessary for applications demanding the highest performance. the current consumption of this group increases from about 160 ma at a system clock of 700 mhz to about 205 ma at a system clock of 1 ghz. there is also a slight (~5%) increase as f out increases from 50 mhz to 400 mhz. avdd (pin 11, pin 19, pin 23, pin 24, pin 36, pin 42, pin 44, and pin 45) these pins can be grouped together and should be isolated from other 1.8 v supplies. a separate regulator is recommended. at a minimum, a ferrite bead should be used for isolation. avdd (pin 53) this 1.8 v supply consumes about 40 ma. the supply can be run off the same regulator as the 1.8 v avdd group, with a ferrite bead to isolate pin 53 from the rest of the 1.8 v avdd group. however, for applications demanding the highest performance, a separate regulator is recommended. avdd (pin 25, pin 26, pin 29, and pin 30) these system clock pll power pins should be grouped together and isolated from other 1.8 v avdd supplies. at a minimum, it is recommended that pin 25 and pin 30 be tied together and isolated from the aggregate avdd 1.8 v supply with a ferrite bead. likewise, pin 26 and pin 29 can also be tied together, with a ferrite bead isolating them from the same aggregate 1.8 v supply. the loop filter for the system clock pll should directly connect to pin 26 and pin 29 (see figure 46 ). applications demanding the highest performance may need to have these four pins powered by their on their own ldo. if the system clock pll is bypassed, the loop filter pin (pin 31) should be pulled down to analog ground using a 1 k resistor. pin 25, pin 26, pin 29, and pin 30 should be included in the large 1.8 v avdd power supply group. in this mode, isolation of these pins is not critical, and these pins consume almost no power.
ad9912 rev. f | page 27 of 40 serial control port the ad9912 serial control port is a flexible, synchronous, serial communications port that allows an easy interface with many industry-standard microcontrollers and microprocessors. single or multiple byte transfers are supported, as well as msb first or lsb first transfer formats. the ad9912 serial control port can be configured for a single bidirectional i/o pin (sdio only) or for two unidirectional i/o pins (sdio and sdo). note that all serial port operations (such as the frequency tuning word update) depend on the presence of the dac system clock. serial control port pin descriptions sclk (serial clock) is the serial shift clock. this pin is an input. sclk is used to synchronize serial control port reads and writes. write data bits are registered on the rising edge of this clock, and read data bits are registered on the falling edge. this pin has an internal pull-down resistor. sdio (serial data input/output) is a dual-purpose pin and acts as input only or input/output. the ad9912 defaults to bidirectional pins for i/o. alternatively, sdio can be used as a unidirectional i/o pin by writing to the sdo active bit (register 0x0000, bit 0 = 1). in this case, sdio is the input, and sdo is the output. sdo (serial data out) is used only in the unidirectional i/o mode (register 0x0000, bit 0 = 1) as a separate output pin for reading back data. bidirectional i/o mode (using sdio as both input and output) is active by default (sdo active bit: register 0x0000, bit 0 = 0). csb (chip select bar) is an active low control that gates the read and write cycles. when csb is high, sdo and sdio are in a high impedance state. this pin is internally pulled up by a 100 k resistor to 3.3 v. it should not be left floating. see the operation of serial control port section on the use of the csb in a communication cycle. 06763-041 ad9912 serial control port sclk (pin 64) sdio (pin 63) sdo (pin 62) csb (pin 61) figure 49. serial control port operation of serial control port framing a communication cycle with csb a communication cycle (a write or a read operation) is gated by the csb line. csb must be brought low to initiate a communica- tion cycle. csb stall high is supported in modes where three or fewer bytes of data (plus the instruction data) are transferred ([w1:w0] must be set to 00, 01, or 10; see table 9 ). in these modes, csb can temporarily return high on any byte boundary, allowing time for the system controller to process the next byte. csb can go high on byte boundaries only and can go high during either part (instruction or data) of the transfer. during this period, the serial control port state machine enters a wait state until all data has been sent. if the system controller decides to abort the transfer before all of the data is sent, the state machine must be reset by either completing the remaining transfer or by returning the csb low for at least one complete sclk cycle (but fewer than eight sclk cycles). raising the csb on a nonbyte boundary terminates the serial transfer and flushes the buffer. in the streaming mode ([w1:w0] = 11), any number of data bytes can be transferred in a continuous stream. the register address is automatically incremented or decremented (see the msb/lsb first transfers section). csb must be raised at the end of the last byte to be transferred, thereby ending the stream mode. communication cycleinstruction plus data there are two parts to a communication cycle with the ad9912. the first writes a 16-bit instruction word into the ad9912, coin- cident with the first 16 sclk rising edges. the instruction word provides the ad9912 serial control port with information regarding the data transfer, which is the second part of the communication cycle. the instruction word defines whether the upcoming data transfer is a read or a write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. write if the instruction word is for a write operation (i15 = 0), the second part is the transfer of data into the serial control port buffer of the ad9912. the length of the transfer (1, 2, or 3 bytes, or streaming mode) is indicated by two bits ([w1:w0]) in the instruction byte. the length of the transfer indicated by [w1:w0] does not include the 2-byte instruction. csb can be raised after each sequence of eight bits to stall the bus (except after the last byte, where it ends the cycle). when the bus is stalled, the serial transfer resumes when csb is lowered. stalling on nonbyte boundaries resets the serial control port. there are three types of registers on the ad9912: buffered, live, and read only. buffered (also referred to as mirrored) registers require an i/o update to transfer the new values from a temporary buffer on the chip to the actual register and are marked with an m in the type column of the register map. toggling the io_update pin or writing a 1 to the register update bit (register 0x0005, bit 0) causes the update to occur. because any number of bytes of data can be changed before issuing an update command, the update simultaneously enables all register changes that have occurred since any previous update. live registers do not require i/o update; they update immediately after being written. read-only registers ignore write commands and are marked ro in the type column of the register map. an ac in this column indicates that the register is autoclearing.
ad9912 rev. f | page 28 of 40 read if the instruction word is for a read operation (i15 = 1), the next n 8 sclk cycles clock out the data from the address specified in the instruction word, where n is 1, 2, 3, or 4, as determined by [w1:w0]. in this case, 4 is used for streaming mode where four or more words are transferred per read. the data readback is valid on the falling edge of sclk. the default mode of the ad9912 serial control port is bidirec- tional mode, and the data readback appears on the sdio pin. it is possible to set the ad9912 to unidirectional mode by writing to the sdo active bit (register 0x0000, bit 0 = 1), and in that mode, the requested data appears on the sdo pin. by default, a read request reads the register value that is cur- rently in use by the ad9912. however, setting register 0x0004, bit 0 = 1 causes the buffered registers to be read instead. the buffered registers are the ones that take effect during the next i/o update. 06763-042 ad9912 core update registers toggle io_update pin s cl k sdio sdo csb serial control port control registers register buffers figure 50. relationship between serial control port register buffers and control registers of the ad9912 the ad9912 uses register 0x0000 to register 0x0509. although the ad9912 serial control port allows both 8-bit and 16-bit instructions, the 8-bit instruction mode provides access to five address bits (a4 to a0) only, which restricts its use to address space 0x00 to address space 0x31. the ad9912 defaults to 16-bit instruction mode on power-up, and the 8-bit instruction mode is not supported. the instruction word (16 bits) the msb of the instruction word is r/ w , which indicates whether the instruction is a read or a write. the next two bits, [w1:w0], are the transfer length in bytes. the final 13 bits are the address ([a12:a0]) at which to begin the read or write operation. for a write, the instruction word is followed by the number of bytes of data indicated by bits[w1:w0], which is interpreted according to table 9 . bits[a12:a0] select the address within the register map that is written to or read from during the data transfer portion of the communications cycle. the ad9912 uses all of the 13-bit address space. for multibyte transfers, this address is the starting byte address. table 9. byte transfer count w1 w0 bytes to transfer (excluding the 2-byte instruction) 0 0 1 0 1 2 1 0 3 1 1 streaming mode msb/lsb first transfers the ad9912 instruction word and byte data can be msb first or lsb first. the default for the ad9912 is msb first. the lsb first mode can be enabled by writing a 1 to the lsb first bit in the serial configuration register and then issuing an i/o update. immediately after the lsb first bit is set, all serial control port operations are changed to lsb first order. when msb first mode is active, the instruction and data bytes must be written from msb to lsb. multibyte data transfers in msb first format start with an instruction byte that includes the register address of the most significant data byte. subsequent data bytes must follow in order from high address to low address. in msb first mode, the serial control port internal address generator decrements for each data byte of the multibyte transfer cycle. when lsb first = 1 (lsb first), the instruction and data bytes must be written from lsb to msb. multibyte data transfers in lsb first format start with an instruction byte that includes the register address of the least significant data byte followed by multiple data bytes. the serial control port internal byte address generator increments for each byte of the multibyte transfer cycle. the ad9912 serial control port register address decrements from the register address just written toward 0x0000 for multibyte i/o operations if the msb first mode is active (default). if the lsb first mode is active, the serial control port register address increments from the address just written toward 0x1fff for multibyte i/o operations. unused addresses are not skipped during multibyte i/o operations. the user should write the default value to a reserved register and should write only zeros to unmapped registers. note that it is more efficient to issue a new write command than to write the default value to more than two consecutive reserved (or unmapped) registers.
ad9912 rev. f | page 29 of 40 table 10. serial control port, 16- bit instruction word, msb first msb lsb i15 i14 i13 i12 i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1 i0 r/ w w1 w0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 6763-043 csb sclk don't care sdio a12 w0w1 r/w a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 don't care don't care don't care 16-bit instruction header register (n) data register (n ? 1) data figure 51. serial control port write?msb fi rst, 16-bit instruct ion, two bytes data cs sclk sdio sdo register (n) data 16-bit instruction header register (n ? 1) data register (n ? 2) data register (n ? 3) data a12 w0 w1 r/w a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 don't care don't care don't care don't care d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 06763-057 figure 52. serial control port read?msb fi rst, 16-bit instruction, four bytes data 06763-045 t s don't care don't care w1w0a12a11a10a9a8a7a6a5d4d3d2d1d0 don't care don't care r/w t ds t dh t hi t lo t clk t h csb sclk sdio figure 53. serial control port write?msb firs t, 16-bit instruction, timing measurements 06763-046 data bit n ? 1 data bit n csb sclk sdio sdo t dv figure 54. timing diagram for serial control port register read 0 6763-047 csb sclk don't care don't care 16-bit instruction header register (n) data register (n + 1) data sdio don't care don't care a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 d1d0r/w w1w0 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 figure 55. serial control port write?lsb fi rst, 16-bit instruction, two bytes data
ad9912 rev. f | page 30 of 40 06763-048 csb sclk sdio t high t low t clk t s t ds t dh t h bit n bit n + 1 figure 56. serial control port timingwrite table 11. definitions of terms used in serial control port timing diagrams parameter description t clk period of sclk t dv read data valid time (time from falling edge of sclk to valid data on sdio/sdo) t ds setup time between data and rising edge of sclk t dh hold time between data and rising edge of sclk t s setup time between csb and sclk t h hold time between csb and sclk t hi minimum period that sclk should be in a logic high state t lo minimum period that sclk should be in a logic low state
ad9912 rev. f | page 31 of 40 i/o register map all address and bit locations that are left blank in table 12 are unused. table 12. addr (hex) type 1 name bit 7 bit 6 bit 5 bi t 4 bit 3 bit 2 bit 1 bit 0 default (hex) serial port configuration and part identification 0x0000 serial config. sdo active lsb first (buffered) soft reset long instruction long instruction soft reset lsb first (buffered) sdo active 0x18 0x0001 reserved 0x00 0x0002 ro part id part id 0x02 0x0003 ro 0x19 0x0004 serial options read buffer register 0x00 0x0005 ac register update 0x00 power-down and reset 0x0010 power- down and enable pd hstl driver enable cmos driver enable output doubler pd sysclk pll full pd digital pd 0xc0 or 0xd0 0x0011 reserved 0x00 0x0012 m, ac reset dds reset 0x00 0x0013 m pd fund dds s-div/2 reset s-divider reset 0x00 system clock 0x0020 n-divider n-divider, bits[4:0] 0x12 0x0021 reserved 0x00 0x0022 pll parameters vco auto range 2 refer- ence vco range charge pump current, bits[1:0] 0x04 cmos output divider (s-divider) 0x0100 reserved 0x30 0x0101 to 0x0103 reserved 0x00 0x0104 and 0x0105 s-divider s-divider, bits[15:0] lsb: register 0x0104 0x00 0x0106 falling edge triggered s-divider/2 0x01 frequency tuning word 0x01a0 to 0x01a5 reserved 0x00 0x01a6 m ftw0 (frequency tuning word) ftw0, bits[47:0] lsb: register 0x01a6 0x00 0x01a7 m 0x00 0x01a8 m 0x00 0x01a9 m 0x00 0x01aa m start-up cond. 0x01ab m start-up cond. 0x01ac m phase dds phase word, bits[7:0] 0x00 0x01ad m dds phase word, bits[13:8] 0x00 doubler and output drivers 0x0200 hstl driver opol (polarity) hstl output doubler, bits[1:0] 0x05 0x0201 cmos driver cmos mux 0x00
ad9912 rev. f | page 32 of 40 addr (hex) type 1 name bit 7 bit 6 bit 5 bi t 4 bit 3 bit 2 bit 1 bit 0 default (hex) calibration (user-accessible trim) 0x0400 to 0x040a reserved 0x00 0x040b dac full- scale current dac full-scale current, bits[7:0] 0xff 0x040c dac full-scale current, bits[9:8] 0x01 0x040d reserved 0x00 0x040e reserved 0x10 0x040f and 0x0410 reserved 0x00 harmonic spur reduction 0x0500 m spur a hsr-a enable amplitude gain 2 spur a harmonic, bits[3:0] 0x00 0x0501 m spur a magnitude, bits[7:0] 0x00 0x0503 m spur a phase, bits[7:0] 0x00 0x0504 m spur a phase, bit 8 0x00 0x0505 m spur b hsr-b enable amplitude gain 2 spur b harmonic, bits[3:0] 0x00 0x0506 m spur b magnitude, bits[7:0] 0x00 0x0508 m spur b phase, bits[7:0] 0x00 0x0509 m spur b phase, bit 8 0x00 1 types of registers: m = mirrored (also called buffered). this type of register needs an i/o update for the new value to take e ffect; ro = read-only; ac = autoclear.
ad9912 rev. f | page 33 of 40 i/o register descriptions serial port configuration (reg ister 0x0000 to register 0x0005) register 0x0000serial port configuration table 13. bits bit name description [7:4] these bits are the mirror image of bits[3:0]. 3 long instruction read-only; the ad 9912 supports only lo ng instructions. 2 soft reset resets register map, except for register 0x0000. setting this bit forces a soft reset, meaning that s1 to s4 are not tristated, nor is their state read when th is bit is cleared. the ad9912 assumes the values of s1 to s4 that were present during the last hard reset. this bit is not self-clearing, and all other registers are restored to their default values after a soft reset. 1 lsb first sets bit order for serial port. 1 = lsb first. 0 = msb first. i/o update must occur for the msb first to take effect. 0 sdo active enables sdo pin. 1 = sdo pin enabled (4-wire serial port mode). 0 = 3-wire mode. register 0x0001reserved register 0x0002 and register 0x0003part id (read-only) register 0x0004serial options table 14. bits bit name description 0 read buffer register for buffered registers, serial port readback reads from actual (active) registers instead of the buffer. 1 = reads the buffered values that take effect during the next i/o update. 0 = reads values that are currently in effect. register 0x0005serial options (self clearing) table 15. bits bit name description 0 register update software access to the register update pin function. writing a 1 to this bit is identical to performing an i/o update. power-down and reset (register 0x0010 to register 0x0013) register 0x0010power -down and enable power-up default is defined by the start-up pins. table 16. bits bit name description 7 pd hstl driver powers down hstl output driver. 1 = hstl driver powered down. 6 enable cmos driver powe rs up cmos output driver. 1 = cmos driver on. 5 enable output doubler powers up output clock generator double r. output doubler must still be enabled in register 0x0200. 4 pd sysclk pll system clock multiplier power-down. 1 = system clock multiplier powered down. if the s4 pin is tied high at power-up or reset, this bit is set, and the defa ult value for register 0x0010 is d0, not c0. 1 full pd setting this bit is identical to activating the pd pi n and puts all blocks (except serial port) into power- down mode. sysclk is turned off. 0 digital pd removes clock from most of digital section; leave serial port usable. in contrast to full pd, setting this bit does not debias inputs, allowing for quick wake-up.
ad9912 rev. f | page 34 of 40 register 0x0011reserved register 0x0012reset (autoclearing) to reset the entire chip, the user can use the (non-autoclearing) soft reset bit in register 0x0000. table 17. bits bit name description 0 dds reset reset of the direct digital synthesis block. reset of this block is very seldom needed. register 0x0013reset (conti nued) (not autoclearing) table 18. bits bit name description 7 pd fund dds setting this bit powers down the dds fundamental outp ut but not the spurs. it is used during tuning of the spurkiller circuit. 3 s-div/2 reset asynchronous reset for s prescaler. 1 s-divider reset synchronous (to s-divider pr escaler output) reset for integer divider. system clock (register 0x0020 to register 0x0022) register 0x0020n-divider table 19. bits bit name description [4:0] n-divider these bits set the feedback divider for system cloc k pll. there is a fixed divide-by-2 preceding this block, as well as an offset of 2 added to this valu e. therefore, setting this register to 00000 translates to an overall feedback divider ratio of 4. see figure 45 . register 0x0021reserved register 0x0022pll parameters table 20. bits bit name description 7 vco auto range automatic vco range selection. enabling this bit allows bit 2 of this register to be set automatically. [6:4] reserved reserved. 3 2 reference enables a frequency doubler prior to the sysclk pll an d can be useful in reducing jitter induced by the sysclk pll. see figure 44 . 2 vco range selects low range or high range vco. 0 = low range (700 mhz to 810 mhz). 1 = high range (900 mhz to 1000 mhz). for system clock settings between 810 mhz and 900 mhz, use the vco auto range (bit 7) to set the correct vco range automatically. [1:0] charge pump current charge pump current. 00 = 250 a. 01 = 375 a. 10 = off. 11= 125 a.
ad9912 rev. f | page 35 of 40 cmos output divider (s -divider) (register 0x 0100 to register 0x0106) register 0x0100 to re gister 0x0103reserved register 0x0104s-divider table 21. bits bit name description [7:0] s-divider cmos output divider. divide ratio = 1 ? 65,536. if the desired s-divider setting is greater than 65, 536, or if the signal on fdbk_in is greater than 400 mhz, then bit 0 in register 0x0106 must be set. note that the actual s-divider is the value in this register plus 1; so to have an s-divider of 1, register 0x0104 and register 0x0105 must both be 0x00. register 0x0104 is the least significant byte. register 0x0105s-divider (continued) table 22. bits bit name description [15:8] s-divider cmos output divider. divide ratio = 1 ? 65,536. if the desired s-divider setting is greater than 65, 536, or if the signal on fdbk_in is greater than 400 mhz, then bit 0 in register 0x0106 must be set. note that the actual s-divider is the value in this register plus 1; so to have an s-divider of 1, register 0x0104 and register 0x0105 must both be 0x00. register 0x104 is the least significant byte. register 0x0106s-divider (continued) table 23. bits bit name description 7 falling edge triggered setting this bit in verts the reference clock before s-divider. [6:1] reserved reserved. 0 s-divider/2 setting this bit enables an addi tional /2 prescaler. see the cmos output divider (s-divider) section. if the desired s-divider setting is greater than 65,536, or if the signal on fdbk_in is greater than 400 mhz, this bit must be set. frequency tuning word (registe r 0x01a0 to register 0x01ad) register 0x01a0 to register 0x01a5reserved register 0x01a6ftw0 (frequency tuning word) table 24. bits bit name description [7:0] ftw0 these registers contain the ftw (frequency tuning word) for the dds. the ftw determines the ratio of the ad9912 output frequency to its dac system cloc k. register 0x01a6 is the least significant byte of the ftw. note that the power-up default is define d by start-up pin s1 to pin s4. updates to the ftw results in an instantaneous frequency jump but no phase discontinuity. register 0x01a7ftw0 (frequen cy tuning word) (continued) table 25. bits bit name description [15:8] ftw0 these registers contain the ftw (frequency tuning word) for the dds. the ftw determines the ratio of the ad9912 output frequency to its dac system cloc k. register 0x01a6 is the least significant byte of the ftw. note that the power-up default is define d by start-up pin s1 to pin s4. updates to the ftw results in an instantaneous frequency jump but no phase discontinuity. register 0x01a8ftw0 (frequen cy tuning word) (continued) table 26. bits bit name description [23:16] ftw0 these registers contain the ftw (frequency tuning word) for the dds. the ftw determines the ratio of the ad9912 output frequency to its dac system cloc k. register 0x01a6 is the least significant byte of the ftw. note that the power-up default is define d by start-up pin s1 to pin s4. updates to the ftw results in an instantaneous frequency jump but no phase discontinuity.
ad9912 rev. f | page 36 of 40 register 0x01a9ftw0 (frequen cy tuning word) (continued) table 27. bits bit name description [31:24] ftw0 these registers contain the ftw (frequency tuning word) for the dds. the ftw determines the ratio of the ad9912 output frequency to its dac system cl ock. register 0x01a6 is the least significant byte of the ftw. note that the power-up default is defined by start-up pin s1 to pin s4. updates to the ftw results in an instantaneous freq uency jump but no phase discontinuity. register 0x01aaftw0 (frequen cy tuning word) (continued) table 28. bits bit name description [39:32] ftw0 these registers contain the ftw (frequency tuning word) for the dds. the ftw determines the ratio of the ad9912 output frequency to its dac system cl ock. register 0x01a6 is the least significant byte of the ftw. note that the power-up default is defined by start-up pin s1 to pin s4. updates to the ftw results in an instantaneous freq uency jump but no phase discontinuity. register 0x01abftw0 (frequen cy tuning word) (continued) table 29. bits bit name description [47:40] ftw0 these registers contain the ftw (frequency tuning word) for the dds. the ftw determines the ratio of the ad9912 output frequency to its dac system cl ock. register 0x01a6 is the least significant byte of the ftw. note that the power-up default is defined by start-up pin s1 to pin s4. updates to the ftw results in an instantaneous freq uency jump but no phase discontinuity. register 0x01acphase table 30. bits bit name description [7:0] dds phase word allows the user to vary the phase of the dds output. see the direct digital synthesizer section. register 0x01ac is the least significant byte of th e phase offset word (pow). note that a momentary phase discontinuity may occur as the phase passes through 45 intervals. register 0x01adp hase (continued) table 31. bits bit name description [13:8] dds phase word allows the user to vary the phase of the dds output. see the direct digital synthesizer section. register 0x01ac is the least significant byte of th e phase offset word (pow). note that a momentary phase discontinuity may occur as the phase passes through 45 intervals.
ad9912 rev. f | page 37 of 40 doubler and output drivers (reg ister 0x0200 to register 0x0201) register 0x0200hstl driver table 32. bits bit name description 4 opol output polarity. setting this bit inverts the hstl driver output polarity. [3:2] reserved reserved. [1:0] hstl output double r hstl output doubler. 01 = doubler disabled. 10 = doubler enabled. when using doubler, bit 5 in register 0x0010 must also be set to 1. register 0x0201cmos driver table 33. bits bit name description 0 cmos mux this bit allows the user to select whethe r the cmos driver output is divided by the s-divider. 0 = s-divider input sent to cmos driver. 1 = s-divider output sent to cmos driver. see figure 39 . calibration (user-accessible trim) (register 0x0400 to register 0x0410) register 0x0400 to register 0x040areserved register 0x040bdac full-scale current table 34. bits bit name description [7:0] dac full-scale current dac full-scale current, bits[7:0]. see the digital-to-analog (dac) output section. register 0x040cdac full-scale current (continued) table 35. bits bit name description [9:8] dac full-scale current dac full-scale current, bits[9:8]. see register 0x040b. register 0x040d to re gister 0x0410reserved harmonic spur reduction (register 0x0500 to register 0x0509) see the harmonic spur reduction section. register 0x0500spur a table 36. bits bit name description 7 hsr-a enable harmonic spur reduction a enable. 6 amplitude gain 2 setting this bit doub les the gain of the cancelling circuit and also doubles the minimum step size. [5:4] reserved reserved. [3:0] spur a harmonic spur a harmonic 1 to spur a harmon ic 15. allows user to choose which harmonic to eliminate. register 0x0501spur a (continued) table 37. bits bit name description [7:0] spur a magnitude linear multiplier for spur a magnitude.
ad9912 rev. f | page 38 of 40 register 0x0503spur a (continued) table 38. bits bit name description [7:0] spur a phase linear offset for spur b phase. register 0x0504spur a (continued) table 39. bits bit name description [8] spur a phase linear offset for spur a phase. register 0x0505spur b table 40. bits bit name description 7 hsr-b enable harmonic spur reduction b enable. 6 amplitude gain 2 setting this bit doub les the gain of the cancelling circuit and also doubles the minimum step size. [5:4] reserved reserved. [3:0] spur b harmonic spur b harmonic 1 to spur b harmon ic 15. allows user to choose which harmonic to eliminate. register 0x0506spur b (continued) table 41. bits bit name description [7:0] spur b magnitude linear multiplier for spur b magnitude. register 0x0508spur b (continued) table 42. bits bit name description [7:0] spur b phase linear offset for spur b phase. register 0x0509spur b (continued) table 43. bits bit name description 8 spur b phase linear offset for spur b phase.
ad9912 rev. f | page 39 of 40 outline dimensions compliant to jedec standards mo-220-vmmd-4 062209-a 0.25 min 1 64 16 17 49 48 32 33 0.50 0.40 0.30 0.50 bsc 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 7.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max seating plane pin 1 indicator 5.36 5.21 sq 5.06 pin 1 indicator 0.30 0.23 0.18 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. top view exposed pad bottom view 9.10 9.00 sq 8.90 8.85 8.75 sq 8.65 figure 57. 64-lead lead frame chip scale package [lfcsp_vq] 9 mm 9 mm body, very thin quad (cp-64-7) dimensions shown in millimeters ordering guide model 1 temperature range package description package option AD9912ABCPZ ?40c to +85c 64-lead lead frame chip scale package [lfcsp_vq] cp-64-7 AD9912ABCPZ-reel7 ?40c to +85c 64-lead lead frame chip scale package [lfcsp_vq] cp-64-7 ad9912a/pcbz evaluation board 1 z = rohs compliant part.
ad9912 rev. f | page 40 of 40 notes ?2007C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d06763-0-6/10(f)

▲Up To Search▲

Price & Availability of AD9912ABCPZ

	To Download AD9912ABCPZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .